With advances in microelectronic technology, many computer systems have shrunk to the size where they can be operated by batteries. In order to extend the life of such battery driven systems, it is often necessary to conserve power consumed by the components that comprise the system. In an effort to conserve power, designers have attempted to use low power systems and to turn off subsystems when they are not required. With low-power CMOS circuits, turning off the clock to a circuit will frequently reduce the power consumed by that circuit by several orders of magnitude.
With computer designs where subsystems are turned off, there is an inherent problem with restarting such subsystems. Computer systems generally operate from a common clock. So, all of the activities of the system occur on the change of state of the clock.
When the clock in a subsystem is disabled, it is a requirement that the subsystem be presented a reliable and stable clock signal internally when said clock is reenabled. In general, an event triggering the reenabling of the clock is asynchronous to the clock. A problem arises if the subsystem is reenabled at or about the same time as the system clock is changing state. It is well known that microelectronic components, in particular the D-type flip-flops which are common in microelectronic systems, can be driven into a metastable state if a narrow clock pulse is applied to such D-type flip-flops. It is highly desirable to avoid such occurrences since an unstable clock signal introduced into a subsystem could have a ripple effect throughout the subsystem causing the subsystem to fail and perhaps the entire computer system to fail.
Accordingly, it is an object of this invention to provide a stable and reliable internal clock signal within a component under all operating conditions, while not requiring any clock whatsoever when the clock is disabled.
It is another object of the invention to provide a stable and reliable clock signal to a component in a computer system when a previously disabled clock signal is restarted asynchronously to the clock.
Prior systems have included the ability to enable a clock going to a subsystem, provided that the clock control circuit was itself always provided with a valid clock. This invention differs by providing a "bootstrapping" method, allowing the clock to be removed from the entire subsystem. In the context of an integrated circuit, this significantly reduces the standby power of the circuit, by allowing the system clock to be disabled at the input pin of the device when the integrated circuit is in a standby mode.